parMERASA

Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

T-CREST/parMERASA/CERTAINTY Workshop

10 July 2014, Madrid, Spain

T-CREST: Time-predictable Multi-Core Architecture for Embedded Systems
parMERASA: Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability
CERTAINTY: Certification of Real time applications designed for mixed criticality

Venue:

UPM, where the ECRTS workshops will be held.

Details on the following ECRTS pages:

  • Local info
  • Map showing UPM and conference hotel



Workshop Program:


Introduction to T-CREST, parMERASA, and CERTAINTY

09:00  T-CREST: Time-predictable Multi-Core Architecture for Embedded Systems
Martin Schoeberl, Technical University of Denmark

09:20  parMERASA Overview - Objectives and Achievements
parMERASA Overview - Objectives and Achievements

09:40  CERTAINTY: Certification of Real time applications designed for mixed criticality
M. Faugère, THALES Research and Technology, France

10:00  Dynamic Budgeting for Settling DRAM Contention of Co-running Mixed-Criticality Applications
           on Multicores
Martin Stigge, Uppsala University, Sweden

10:20  Break


T-CREST

10:40  Improving the average-case using worst-case aware prefetching
Jamie Garside, University of York

11:00  Argo: A Real-Time Network-on-Chip Architecture with an Efficient GALS Implementation
Evangelia Kasapaki, Technical University of Denmark

11:20  Function Splitting for the Patmos Method Cache
Stefan Hepp, Vienna University of Technology

11:40  Single-Path Code Generation and Input-Data Dependence Analysis
Daniel Prokesch, Vienna University of Technology

12:00  Time-Predictable Caching of Stack Data
Sahar Abbaspourseyedi, Technical University of Denmark

12:20  Branching in the time-predictable processor Patmos
Wolfgang Puffitsch, Technical University of Denmark

12:40  Lunch


parMERASA

13:40  Systematic and Timing-analyzable Parallelization of Industrial Applications
Martin Frieb, University of Augsburg, Germany

14:00  Towards Parallelization of Automotive Legacy Software
Sebastian Kehr, Denso Deutschland GmbH

14:20  Static timing analysis of parallel applications
Haluk Ozaktas or Christine Rochange, University of Toulouse, France

14:40  Multi-core architectures for hard real-time systems
Milos Panic, Barcelona Supercomputing Center, Spain

15:00  Break


CERTAINTY

15:20  Scheduling, mapping and interference analysis for mixed-critical applications
           on multi-core platforms
Nikolay Stoimenov, Eidgenössische Technische Hochschule Zürich, Switzerland

15:40  Composability and scheduling
Petro Poplavko, Verimag, France

16:00  NoC modeling and computation of worst-case traversal bounds on MPPA
B. Dinechin, Kalray, France

16:20  Fault modeling at NoC level
A. Tschiene, Technische Universität Braunschweig, Germany

16:40  Static Code-Level Timing and Stack Usage Analysis; Tool demo
C. Ferdinand, Absint, Germany

parMERASA is an FP-7 project
of the European Union

Project Ref.:

Start Date:

End Date:

Duration:

Project Cost:

Project Funding:

Project Status:

287519

2011-10-01

2014-09-30

36 months

4.58 million €

3.3 million €

Ended

parMERASA is a follow-up
on the FP-7 project MERASA.